The problem in the new semiconductor technologies is that the DC power (leakage of the transistors) is growing because the devices get smaller and the AC power is growing because of higher frequencies and their respective voltage.
A number of commercial computer processors (CPU: central processing unit) nowadays offer dynamic voltage and frequency scaling (DVS) as a mechanism to reduce or limit power consumption. Examples include Enhanced SpeedStep® technology in Intel processors, PowerNow!™ in AMD processors, and PowerTune® in IBM PowerPC® 970.
There is significant prior art that proposes schemes that use CPU utilization to determine when to use DVS without reducing or reducing excessively the computing system's performance. Low CPU utilization at the lowest frequency is considered as indicative of a low performance requirement, which, in turn, lets the system use a lower operating point, thereby saving power. High CPU utilization at a lower operating point would be considered indicative of higher demand for processor cycles and consequently interpreted as a situation when a higher operating point could improve performance.
Other schemes for determining the right operating point to use for particular workloads and workload mixes use off-line characterization of workload behaviour or a general expectation from the type of workload. For example, running compute-intensive applications would cause the CPU to use a higher operating point while running user-interaction dominated applications would cause the CPU to use a lower operating point.
In all proposed and implemented approaches, DVS is exploited primarily for power savings with user-specified, application-specified or system-inferred measures to estimate the CPU requirements.
Therefore, to manage the power dissipation of microprocessors effectively, it is very important to dynamically change the frequency which allows either the voltage to follow the frequency change as fast as possible or to stabilize the voltage on the chip by only changing the frequency.
Possible solutions known for dynamically changing the frequency are slewing a reference frequency which feds a digital phase locked loop device (PLL) and by this way changing the frequency of the devices attached to it. The speed of changing the frequency is limited by the bandwidth of the PLL. Typically, only changes of frequencies are allowed in the millisecond (ms) region, whereas for the DVS power management method changes in the sub nanosecond (ns) region are necessary.